With the continuous development of communication technologies, users have increasingly high requirements for the quality of service such as capacity and speed of the communication. Access network is one of the most challenging the region in the entire telecommunication network. To satisfy the users' demand for the bandwidth, and to realize a high-speed, broadband, and intelligent access network, different access technologies have been proposed one after another. Among those access technologies, the most promising one is the passive optical network (PON) technology, especially the Ethernet passive optical network (EPON) technology.
The EPON technology is mainly characterized in a simple maintenance, low cost, high transmission bandwidth, and high price performance ratio. In particular, the EPON technology provides a bandwidth of 1 GHz or even 10 GHz, which make it possible that realizes the synchronous transmission of voice, data, and video services.
The EPON is a passive optical transmission technology, without using components having amplification and relay functions. Therefore, the transmission distance and number of branches of the EPON network depend on the power budget and various transmission losses. With the increase of the transmission distance or number of branches, a signal noise ratio (SNR) of the data transmission decreases gradually, which leads to more bit errors. To solve this problem, a forward error correction (FEC) technology is introduced into the EPON system to improve the interference resistance capability of the system, so as to increase the power budget of the system.
The basic operating principles of the FEC in the EPON system are as follows: FEC check information bits are appended to Ethernet frames transmitted at a sending end, in which the check information bits are associated with (constrained by) the Ethernet frame data to be checked according to certain determinate rules; and a receiving end checks the relationship between the Ethernet frame data and the check information bits according to predetermined rules, where the relationship is destroyed once an error occurs during transmission, so as to realize the error correction of the Ethernet frame data. The FEC technology strives for correcting maximum possible errors with minimum possible check information bits, so as to achieve an optimal balance between the overhead (caused by the additional check information bits) and the obtained coding gain.
In the EPON system, in order to ensure that the sent data is in a format acceptable to the receiving end, before the FEC technology is performed, a line coding technology needs to be employed. In addition, the line coding must ensure adequate transition (between 0 and 1) of the sent data, so as to enable the receiving end to recover a clock. A line coder further provides a method for aligning data with words, in which a fine direct current (DC) balance is maintained on the line.
Standards associated with the Ethernet system have already employed line coding mechanisms with a higher coding efficiency, such as 64b/66b, in a physical coding sublayer (PCS). The 64b/66b line coding mechanism adds a 2-bit synchronization character to the 64-bit information to serve as a synchronization header, so as to form a 66-bit line coding block. Normally, the 2-bit synchronization character may be only “01” or “10”. The synchronization character of “01” indicates that the 64-bit information is all data information, and the synchronization character of “10” indicates that the 64-bit information contains control information with data information. When the synchronization character is “00” or “11”, it indicates that error occurs during transmission. When the number of line coding blocks after the 64b/66b line coding process reaches a data length required by the FEC coding, the FEC coding is performed. The corresponding check information is generated after the FEC coding. The length of the check information is a multiple of 64, so that the check information blocks formed by check information are in a unit of 64 bits. Then, a 2-bit synchronization character (“00” or “11”) is added at the head of each check information block to serve as a synchronization header of the check information block, so as to form a 66-bit check information block with a check information block synchronization header. For convenience of description, a 64-bit check information block and the 2-bit check information block synchronization header are together referred to as a check block, and the length of one check block is 66 bits.
That is, the lengths of the line coding blocks and check blocks after FEC coding are both 66 bits. Each line coding block contains a 2-bit synchronization header and a 64-bit data information block, in which the two bits of the synchronization header are always different; each check block contains a 2-bit synchronization header and a 64-bit check information block, in which the two bits of the synchronization header are always the same. Thus, the receiving end performs the synchronization based on characteristics of the synchronization headers in the line coding blocks and check blocks, so as to determine the start and end positions of an FEC code word (a complete FEC code word contains several line coding blocks and several check blocks).
Currently, a structure of an FEC code word (the code word contains K line coding blocks and M check blocks) is as shown in FIG. 1. Each line coding block contains a synchronization header having two different bits and a 64-bit data information block Di (i=1, 2, . . . K), and each check block contains a synchronization header having two same bits and a 64-bit check information block Pi (i=1, 2, . . . M). The synchronization header of the first check information block P1 is “00”, and the synchronization header of any other check information blocks Pi (i=2, 3, . . . M) is “11”. Therefore, the receiving end performs an FEC code word synchronization based on characteristics of the synchronization headers.
However, the inventors of the disclosure find that the synchronization headers of the data information blocks may change from the original “01” or “10” to “00” or “11” and the synchronization headers of the check information blocks may also change because of the noise interference in the transmission, so that incorrect synchronization may occur sometimes.
For example, the structure of an FEC code word is described as follows.
(1) The number of data information blocks is K, and the number of check information blocks is M (M=4), and thus, the number of information blocks contained in the FEC code word is N, N=K+M=K+4.
(2) The check information blocks are always added to tail ends of the data information blocks.
(3) Every N information blocks and the corresponding synchronization headers form one FEC code word, and a plurality of FEC code words are connected in a head to tail manner to form a string of information sequence.
As shown in the “incorrect synchronization 1” part of FIG. 2, when one bit in the synchronization header of the Kth (i.e. the (i+K−1)th position in FIG. 2) data information block in the FEC code word has an error, the original “01” or “10” is changed to “00” (i.e. changed to the synchronization header of the first check information block); meanwhile, the synchronization header of the first check information block of the FEC code word is changed from the original “00” to “11” (i.e. changed to the synchronization header of the second check information block); the synchronization header of the second and the third check information blocks remains unchanged and are still “11”; and one bit in the synchronization header of the fourth (i.e. the (i−1)th position in FIG. 2) check information block in the previous FEC code word has an error, that is, the original “11” is changed to “10” or “01” (i.e. changed to a synchronization header of a data information block). At this time, the receiving end mistakes the (i−1)th to (i+K+2)th positions as one FEC code word for synchronization, and performs the synchronization accordingly. Thus, an incorrect synchronization occurs. The “incorrect synchronization 2” in FIG. 2 shows another situation leading to incorrect synchronization, which is different from the incorrect synchronization 1 mainly in that, the positions of the erroneous synchronization characters are different, and will not be described in detail here.
In the “incorrect synchronization 1” as shown in FIG. 2, the FEC code word has four erroneous synchronization bits, so as to result in the incorrect synchronization. Therefore, the number of bits leading to the incorrect synchronization of the FEC code word is four. Of course, while the errors occur in the four bits, the synchronization header of other data information blocks may also have errors so that two bits of the synchronization header both have errors. For example, a synchronization header of a certain data information block is changed from “01” to “10” or from “10” to “01”, and in this case, the number of bits leading to the “incorrect synchronization 1” shown in FIG. 2 is six. However, the probability of the 6 bits errors may be ignored as compared with the probability of the 4 bits errors. Therefore, when the incorrect synchronization is calculated in statistics, only the minimum bit number leading to the incorrect synchronization of the FEC code word needs to be considered; as for the “incorrect synchronization 1” shown in FIG. 2, the minimum bit number is four. The number of check information blocks M=4, the synchronization headers of the check information blocks adopt the sequence of the prior art (that is, 00, 11, 11, 11), and various minimum bit numbers that possibly lead to the incorrect synchronization of the FEC code word are listed in Table 1. If the synchronization start point of the FEC code word is at i, it indicates a correct synchronization as the minimum error bit number at this time is 0. If the synchronization start point of the FEC code word is (i−1), that is the case of “incorrect synchronization 1” in FIG. 2, the minimum error bit number is 4. Other situations are similar to the above descriptions. It should be noted that, the FEC code word repeats once every N information blocks, that is, the information blocks with start points of i, (i+N), and (i−N) all indicate the data information block D1 in the FEC code word.
TABLE 1Start Point of the Synchronized FEC Code Word andCorresponding Minimum Error Bit Number LeadingSynchronization Header ofto Incorrect SynchronizationCheck Information Block(i − 4) to(i + 4) toM = 4P1_hP2_hP3_hP4_h(i − N + 5)i − 3i − 2i − 1ii + 1i + 2i + 3(i + N − 5)Prior Art0 01 11 11 1886404688
That is to say, in the prior art, when one FEC code word has four error synchronization header bits (in three synchronization characters), the incorrect synchronization may occur. Synchronization is the basis of data reception, and the incorrect synchronization may cause error in data reception. However, the probability of incorrect synchronization is still high in the prior art, and an improvement needs to be made to the prior art.